The present invention relates to a semiconductor device and a manufacturing method thereof.
For extending a substantial channel width of a transistor without increasing the size, a technique of forming unevenness such as trenches to a substrate in a channel region has been known.
For example, Japanese Unexamined Patent Publication No. Hei11(1999)-103058 (JP-A-1999-103058) and Japanese Unexamined Patent Publication No. Sho51 (1976)-147269 (JP-A-1976-147269) describe semiconductor devices including transistors of a trench gate structure in which a trench is formed to the surface of a substrate.
Vertical MOS transistors in which a current path is in a longitudinal direction have also been known, which are different from the lateral transistors described in JP-A-1999-103058 and JP-A-1976-147269. Japanese Unexamined Patent Publication No. Hei10 (1998)-32331 (JP-A-1998-32331) describes the configuration of a vertical type MOS transistor. The vertical type MOS transistor involves a problem that a parasitic capacitance defined with an n− electric field relaxation region and a gate electrode by way of a gate oxide film is larger in view of a chip area ratio and a feedback capacitance increases to increase a switching loss compared with that of the lateral MOS transistor. Then, JP-A-1998-32331 describes a configuration of increasing the thickness of the gate insulating film only at the bottom of the trench, which can decrease the parasitic capacitance defined with the n− electric field relaxation region and the gate electrode while keeping a threshold value of the vertical type MOS transistor lower thereby decreasing the switching loss.
Further, Japanese Unexamined Patent Publication No. 2009-88188 (JP-A-2009-77188) also describes a configuration of a vertical MOS transistor. JP-A-2009-77188 describes a configuration of forming a uniformly thick silicon oxide film rounded at the corner at the bottom and the vicinity thereof in a trench formed to an N-type semiconductor layer. On the other hand, a silicon oxide film with a thickness smaller than that of the silicon oxide film at the bottom and the vicinity thereof and rounded at the corner is formed above the side wall of the trench. It is described that the thick silicon oxide film decreases the gate capacitance, the thin silicon oxide film thereabove can ensure the excellent transistor characteristic, and the roundness at the corner can suppress the generation of crystal defects and disperse the gate electric field to improve the gate voltage withstanding.
Further, Japanese Unexamined Patent Publication No. 2007-81396 (JP-A-2007-81396) describes an MOS transistor having a semiconductor substrate having a main surface of a (100) plane, and describes that a source region and a drain region are arranged on a linear line parallel with the <100> direction.